A chip package is a housing used to encapsulate an integrated circuit die for plugging into (socket mount) or soldering onto (surface mount) a printed circuit board. Most chip packages are constructed with the die mounted on a package substrate with signals from the die connected to conductive lines or traces on the surface of the package. The die or chips within the package may be wire bond or flip-chip interconnected to the die.
FIG. 1 is a cross-section view of a conventional wire bond package. A wire-bond package 10 is constructed with a die 12 mounted on a substrate 14 face-up (can also be face down) with wire bonds 16 connected between bond pads (not shown) on the die 12 and bond pads (or fingers) (not shown) on the package substrate 14.
FIG. 2 is a cross-section view of a conventional flip-chip package. A flip-chip package 20 has solder balls (also known as solder bumps) 22 placed on the (active) surface of the die 24, and the die 24 is “flipped” over onto the package substrate 26 and connected to the package via the solder balls 22. In both FIGS. 1 and 2, after the packages 10 and 20 are assembled, the packages 10 and 20 are surface mounted to a printed circuit (PCB) board 30 by metal leads (not shown) or solder balls 28.
The current trend with both types of package technologies is towards the production of custom chip designs in which a customer contracts with a chip manufacture to produce a custom chip package. There are a number of different types of silicon platforms in existence from which to fabricate the chips. Examples of different types of silicon platforms include FPGA (Field Programmable Grid Array), platform or structured ASICs, and cell-based ASICs. As different silicon platforms become more prevalent, customers are looking for ways to migrate chip designs between platforms in which one type of platform is used for prototyping or limited production, and a lower-cost platform is used to implement high-volume production.
For example, a chip design may be first implemented as an FPGA, which is typically large and expensive, in situations where the design is unproven or demand for the chip is unknown. Once a determination is made to mass-produce the design, the customer may migrate the FPGA design to an ASIC platform, which is an overall lower-cost solution in high-volume environments. Besides converting an existing FPGA design to ASIC, customers may also convert a platform/structured ASIC design to a full cell-based ASIC, for instance.
Rapidchip is another type of silicon platform where a reference chip design serves as a starting point for the design of custom chips. A design produced as a rapidchip may be used as a development vehicle in situations where it is critical to prove a product design or that a market exists for that product. If the market is successful, then the design will be converted to ASIC to lower overall product cost.
When a chip design is redesigned from one silicon platform to another, e.g., from FPGA or platform ASIC to a full cell-based ASIC, the area of the die is dramatically reduced. The result of this die size reduction makes it challenging to interconnect the redesigned die to the package that was designed for the original die. A package has a pin-out comprising pins, leads or balls at fixed locations corresponding to signal I/Os and power and ground. When a chip is redesigned from one silicon platform to another, the locations of those pins have to be the same on a converted package to maintain footprint compatibility. Footprint compatibility enables the customer to use the cost reduced chip design in the existing PCB board. However, assembly rules place limitations on design parameters such as, wire length, wire angle, loop height, wire pitch, bond finger pitch, and radial fan-out. With relatively large die, assembly rules are easier to meet. When a chip is redesigned and made smaller, however, I/O density and routing congestion increases, reducing the possibility of assembly rule compliance. If any of the pin locations of the package need to be altered to accommodate the redesigned die, then footprint compatibility is lost.
FIG. 3 is a diagram illustrating one example of a package design issue that can arise during die migration of a die to a smaller die. A top view of a redesigned die 40 is shown to illustrate that to due assembly rules, a decrease in die size results in reduced signal fan-out. The dashed boundary lines 42 show available radial fan-out angles for the routing of wire bonds from the die 40 to the package substrate. In this example, the fan-out rules are met when all bond wires from the side of the die can be routed to the substrate within the two boundary lines 42. The first three arced lines showing bond wire connection locations on the substrate meet the fan-out rules. Due to the small form factor die, however, some bond wires fan out past the boundary lines 40, resulting in violation of the fan-out rules (assembly rules), as shown by the last arced line. In such a case, the redesigned die 40 may force a redesign of the chip package, resulting in footprint incompatibility.
Losing footprint compatibility with the original chip package in this manner is disadvantageous because the PCB board to which the original chip package was to attach must also be redesigned to accommodate the new package footprint. Such redesigns may add months of engineering time to a project and significantly impact both costs and the time to market.
One solution to avoid having to redesign the PCB board is a daughter card approach in which a daughter card is inserted between the redesigned package and the PCB board to act as a bridge between the old and new connections. This solution is inadequate because it still requires a redesign of the original chip package, and is not cost-effective for high-volume design. In addition, added parasitics to the package may impair the electrical performance of the redesigned die, thus preventing the die from meeting performance capabilities.
Accordingly, what is needed is a method and apparatus that provides an easy migration path from low volume silicon platforms, such as FPGA and platform ASICs, to lower cost silicon platforms, such as cell-based ASICs, while maintaining footprint compatibility with the existing chip package.